With recent advancement of digital technologies, higher functionality of electronic hardware such as portable information devices and home information appliances have been provided. For this reason, demands for an increase in a capacity of a nonvolatile memory element, a reduction in writing electric power in the memory element, a reduction in write/readout time in the memory element, and longer life of the memory element have been increasing.
In response to such demands, it is said that there is a limitation on miniaturization of an existing flash memory using a floating gate. On the other hand, a nonvolatile memory element (resistance variable memory) using a resistance variable layer as a material of a memory portion is formed by a memory element having a simple structure including a resistance variable element. Therefore, further minitualization, a higher-speed, and further electric power saving of the nonvolatile memory element are expected.
When using the resistance variable layer as the material of the memory portion, its resistance value varies from a high-resistance value to a low-resistance value or from the low-resistance value to the high-resistance value, for example, by inputting electric pulses. In this case, it is necessary to clearly distinguish two values, i.e., the high-resistance value and the low-resistance value, to vary the resistance value stably between the low-resistance value and the high-resistance value at a high-speed, and to hold these two values in a nonvolatile manner. For the purpose of stabilization of such a memory property and minitualization of memory elements, a variety of proposals have been proposed in the past.
As one of such proposals, patent document 1 discloses a memory element in which memory cells are formed by resistance variable elements each of which includes two electrodes and a storing layer sandwiched between these electrodes and is configured to reversibly vary a resistance value of the storing layer. FIG. 33 is a cross-sectional view showing a configuration of such a conventional memory element.
As shown in FIG. 33, the memory element has a configuration in which a plurality of resistance variable elements 10 forming memory cells are arranged in array. The resistance variable element 10 has a configuration in which a high-resistance film 2 and an ion source layer 3 are sandwiched between a lower electrode 1 and an upper electrode 4. The high-resistance film 2 and the ion source layer 3 form a storing layer. The storing layer enables data to be stored in the resistance variable element 10 in each memory cell.
The resistance variable elements 10 are disposed above MOS transistors 18 formed on a semiconductor substrate 11. The MOS transistor 18 includes source/drain regions 13 formed in a region separated by an isolation layer 12 inside the semiconductor substrate 11 and a gate electrode 14. The gate electrode 14 also serves as a word line which is one address wire of the memory element.
One of the source/drain regions 13 of the MOS transistor 18 is electrically connected to the lower electrode 1 of the resistance variable element 10 via a plug layer 15, a metal wire layer 16, and a plug layer 17. The other of the source/drain regions 13 of the MOS transistor 18 is connected to the metal wire layer 16 via the plug layer 15. The metal wire layer 16 is connected to a bit line which is the other address wire of the memory element.
By applying electric potentials of different polarities between the lower electrode 1 and the upper electrode 4 of the resistance variable element 10 configured as described above, ion source of the ion source layer 3 forming the storing layer is caused to migrate to the high-resistance layer 2. Or, the ion source is caused to migrate from the high-resistance layer 2 to the upper electrode 4. Thereby, the resistance value of the resistance variable element 10 transitions from a value of a high-resistance state to a value of a low-resistance state, or from a value of the low-resistance state to a value of the high-resistance state, so that data is stored.
A memory element (phase-change type memory) is also known, in which a resistance variable material sandwiched between an upper electrode and a lower electrode forms a first electric pulse varying resistance layer having a polycrystalline structure and a second electric pulse varying resistance layer having a nano crystal or an amorphous structure. The resistance layer formed of the resistance variable material is controlled by varying its resistance value according to a voltage and a pulse width of electric pulses applied, thereby operating as a resistance variable element (see, for example, patent document 2).
Examples using transition metal oxide consisting of two elements, which are different from the resistance variable materials disclosed in Patent documents 1 and 2, are reported. For example, Patent document 3 discloses as the resistance variable material, NiO, V2O5, ZnO, Nb2O5, TiO2, WO3, and CoO. These materials consist of two elements and therefore, composition control therefor and film forming using them are relatively easy. In addition, these materials may have relatively high affinity with a semiconductor manufacturing process.
Patent document 4 discloses a variety of resistance variable materials obtained by the fact that a p-type oxide semiconductor material comprising metal elements has rapid metal-insulator transfer. In particular, specific examples thereof are Ga, As and VO2. Patent document 5 discloses, as examples of a resistance variable material, titanium oxide and Ta2O5 which is tantalum oxide as insulators whose resistance states change, respectively.    Patent document 1: Japanese Laid-Open Patent Application Publication No. 2006-40946    Patent document 2: Japanese Laid-Open Patent Application Publication No. 2004-349689    Patent document 3: Japanese Laid-Open Patent Application Publication No. 2004-363604    Patent document 4: Japanese Laid-Open Patent Application Publication No. 2006-32898    Patent document 5: Japanese Laid-Open Patent Application Publication No. Hei. 7-263647    Non-patent document 1: I. G. Beak Et Al., Tech. Digest IEDM 204, 587 page    Non-patent document 2: Japanese Journal of Applied Physics Vol 145, NO 11, 2006, pp. L3 10-L312 FIG. 2